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# Project Tracker Status Priority Subject Author Assignee Target version
10016 Trace Matcher Task Closed Normal Use Gradle 4.10.3 in build system Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10015 Trace Matcher Feature Closed Normal Report an error when input file is empty Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10009 Verilog Translator Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10002 Fortress Task New Normal get Boolector solver from server as dependency Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
10000 Retrascope Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9999 Castle Task Closed Normal ChangeLog -> ChangeLog.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
9998 Castle Task Closed Normal README -> README.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Verified High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9986 QEMU4V Task New Normal check if QEMU4V features can be implemented as TCG plugin Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9971 MicroTESK for RISC-V Task Closed Normal print Spike trace to separate log file for every JUnit test case Sergey Smolov Sergey Smolov MicroTESK for RISC-V - 0.1 Actions
9964 Retrascope Task Verified Normal add HDL examples to project distribution Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9962 Verilog Translator Bug Verified High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Verified High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9917 QEMU4V Task Closed Normal check QEMU4V-specific code on compliance with coding style Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9911 Retrascope Task Verified Urgent merge "*/sample/*TestCase" Java test cases Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9909 QEMU4V Task Closed Normal migrate to QEMU 4.2.0 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9904 Verilog Translator Task Verified Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9901 Retrascope Test Suite Bug New Low initializationError in some tests after Jenkins update Sergey Smolov Mikhail Lebedev Actions
9899 Verilog Translator Task Verified Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
9889 MicroTESK for Plasma Task Resolved Normal rm deprecated 'findbugs' plugin from Gradle build script Sergey Smolov Actions
9888 Retrascope IDE Task New Normal complete migration from Ant to Gradle build system Sergey Smolov Retrascope IDE - 0.1 Actions
9863 QEMU4V Task Closed Normal use Gradle 4.10.3 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9862 QEMU4V Task Closed Normal migrate to QEMU 4.1.0 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9823 Retrascope IDE Task Verified Normal README.txt -> README Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9822 Verilog Translator Bug Resolved Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9816 Retrascope IDE Bug New Normal Retrascope IDE does not appear in "Installed Software" menu Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9815 Retrascope IDE Task New Normal uninstaller for Retrascope IDE Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9811 Verilog Translator Task Verified High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
9810 Retrascope IDE Task New Normal Gradle build system Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9806 Retrascope Task Closed Normal rm dependency from commons-lang library Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9776 Retrascope IDE Task Verified Normal try to use SVEditor instead of veditor Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9769 Retrascope Feature Closed Normal GraphML printers: make branch values italic Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9767 Retrascope Feature Closed Normal GraphML printers: use dotted arrows for Module->(Module| Process) hierarchy dependencies Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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