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# Project Tracker Status Priority Subject Author Assignee Target version
9806 Retrascope Task Closed Normal rm dependency from commons-lang library Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9776 Retrascope IDE Task Verified Normal try to use SVEditor instead of veditor Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9775 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9769 Retrascope Feature Closed Normal GraphML printers: make branch values italic Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9767 Retrascope Feature Closed Normal GraphML printers: use dotted arrows for Module->(Module| Process) hierarchy dependencies Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
9764 Retrascope IDE Task New High migrate to Eclipse 2019 Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9763 Retrascope Test Suite Bug Closed Normal missing javadoc headers in Java files of 'ru.ispras.retrascope.engine.hldd.printer.smv.spec.sample.vcegar' package Sergey Smolov Mikhail Lebedev Actions
9762 Retrascope Task Closed High prepare to 1.1.1 release Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9726 Retrascope Test Suite Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9658 Retrascope Task Closed Normal Check for duplicated data access conflict assertions Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9607 Retrascope Test Suite Task Closed Normal add QUIP 9.0 benchmark Sergey Smolov Sergey Smolov Actions
9606 Retrascope Test Suite Task Closed Normal add IWLS 2005 benchmark Sergey Smolov Sergey Smolov Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9562 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.usedef.MemStageUseDefSmvPrinterTestCase: model checker crashes without errors in *.smvlog Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9503 Retrascope Feature Closed Normal when debug option is enabled, pass it to the model checker as well Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9488 Retrascope Task New Normal CFG-GADD transformer backend that makes assignments index and range-free Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
9486 Retrascope Feature Closed Normal HDL parser's init_process backend: calculate initial values if possible Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9485 Retrascope Bug Closed Normal missing javadoc Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9484 Retrascope Task Closed Normal Check variables\switches\basic blocks number at HDL parser test cases Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9482 Retrascope RISC-V Benchmark Bug Closed Normal ru.ispras.retrascope.sample.VexRiscvVexRiscvGaddTestCase: ERROR: Wrong number of out edges for 'ru.ispras.retrascope.model.cfg.CfgBlockStatement@c219bf5': 2 Sergey Smolov Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
9474 Retrascope Feature Closed Normal enable\disable backend parameters for all the engines Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9468 Retrascope Feature Closed Normal HDL parser backend that removes 'initial' processes Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9463 Retrascope Bug Closed Normal check if jUnit test cases for CfgCgaaTransformer return same results on different machines\platforms Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9462 Retrascope Task Closed Normal jUnit test cases for HDL parsers that count numbers of CFG processes, statements, etc. Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9457 Retrascope Feature Closed Normal one more auxiliary path in GADD model for terminal endings Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9446 Retrascope Feature Closed Normal Debug output file for engines and their backends Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9438 Retrascope Task Closed Normal jUnit test cases for CFG-GAD transformer that check path number Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9437 MicroTESK Bug Closed Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov Sergey Smolov MicroTESK - 2.4 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9430 Retrascope Task Closed Normal CGAA -> GADD Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9427 Retrascope Task Closed Normal reuse variables' versions upon CGAA model building Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9415 QEMU4V Task Closed Normal migrate to QEMU 3.1.0 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9389 Retrascope Task Closed Normal Assertion -> Property Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9387 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.InstructionBPUTestCase: ../microtesk-powerpc/build/test/instruction_bpu/instruction_bpu_0000.s:47: Error: operand out of range (0x0000000000002774 is not between 0x0000000000000000 and 0x000000000000001 Sergey Smolov Alexander Protsenko Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
9377 MicroTESK for MIPS Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
9374 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.BoundaryTestCase: Simulation failedThe CPR storage is not defined in the model.ru.ispras.microtesk.model.ConfigurationException: The CPR storage is not defined in the model. Sergey Smolov Alexander Protsenko Actions
9373 QEMU4V Task Closed Normal write a PowerPC-related chapter to "Getting Started" Sergey Smolov Maxim Chudnov QEMU4V - 0.3 Actions
9365 QEMU4V Bug Closed Normal missing insn binary images in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9363 QEMU4V Task Closed Normal remove 'set_q4v_tstamp' function calls from RISC-V/MIPS/Aarch64 'cpu_loop.c' modules Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9335 Retrascope Feature Closed Normal cgaa-assert-extractor engine Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9334 QEMU4V Bug Closed Normal timestamp reset at MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9333 QEMU4V Bug Closed Normal unexpected hex value in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9310 Retrascope Task Closed Normal substitute SMT-LIB variables those names are equal to builtin commands Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9291 Retrascope Task Closed Normal use nuXmv 1.1.1 Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9281 Retrascope Feature Closed Normal cmdline option that specifies clock variable for CGAA model Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9280 Retrascope Task Closed Normal prepare the code to 1.1.1 release Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9278 Retrascope Task Closed Normal use CGAA model instead of EFSM-based assertions to get clocks Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9277 Retrascope Task Closed High mv clock-like variable detection to CFG-to-CGAA transformer Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9269 QEMU4V Task Closed Normal migrate to QEMU 3.0.0 Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9264 Retrascope Feature Closed Normal '--disable-backends' cmdline option for HDL parser engine Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9251 Verilog Translator Task Closed High calculate type of index for bit-vector arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9249 Retrascope Task Closed Normal separate jUnit test cases for EfsmGraphMlPrinter engine Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9248 Retrascope Task Closed High CFG model process should not have it's own internal variables Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9247 Retrascope Feature Open High CFG-to-C printer Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
9242 Retrascope Task Closed High check BVEXTRACT operation's parameter order Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9235 Retrascope Test Suite Task Closed Normal adapt JUnit components to new interface of ToolTest class Sergey Smolov Mikhail Lebedev Actions
9232 Verilog Translator Task Closed High remove typedefs from texas97-tests/PPC60X_bus/src/define.v Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
9216 Retrascope Test Suite Task Closed Normal remove tests for Verilog Translator from project Sergey Smolov Mikhail Lebedev Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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