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# Project Tracker Status Priority Subject Author Assignee Target version
6504 Retrascope Bug Closed Normal fifo/fifo.v: nuSMV model checker returns ERROR Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
6510 Retrascope Bug Closed Normal fix javadoc Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
6730 Retrascope Bug Closed Normal fix javadoc Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
6892 Retrascope Bug Closed Normal support for non-zero starting bitvectors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6959 Retrascope IDE Bug Closed High java.lang.NullPointerException at startup Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6984 Retrascope IDE Bug Closed Normal java.io.IOException: Unable to resolve plug-in "platform:/plugin/retrascope-ide/icons/retrascope.gif". Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
7097 Retrascope Bug Closed Normal 32-bit constants should be casted to appropriate values Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7145 Retrascope Bug Closed Normal cfg-rnd-testgen: take variable invariants into account Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7166 Retrascope Bug Closed Normal cfg-rnd-testgen: OutOfMemoryError at b10 (1.000.000 ticks) Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
7474 Verilog Translator Bug Closed Normal missing empty branches for 'if' statements Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7555 Fortress Bug Closed Normal unable to create constraint-related jUnit tests including unused variables Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
7557 Fortress Bug Closed High ConstCastTestCase: java.lang.AssertionError: Calculator failed to substitute result Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
7576 Retrascope Bug Closed Normal mips16/hazard_detection_unit.v: java.lang.IllegalArgumentException: Constraint contains errors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7593 Retrascope Bug Closed Normal mips16\data_mem.v: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7720 Retrascope Bug Closed Normal mips16/data_mem.v: The expression to be computed (ram) contains unevaluated variables: [ram] Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
7753 Retrascope Bug Closed Normal example.vhd: cannot generate SMV-based test Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7883 Retrascope Bug Closed Normal fifo_testbench.v: java.lang.NullPointerException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8237 Retrascope Bug Closed Normal CFG random test generator works too slow on b19 Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8242 Trace Matcher Bug Closed Normal print hexadecimal values to the output file in the same form as they were at input flies Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8244 Retrascope Bug Closed Normal CGAA-to-EFSM engine falls on b05 test Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8245 Retrascope Bug Closed Normal cfg-rnd-testgen: IllegalArgumentException at minimips\pps_pf.v Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8283 Retrascope Bug Closed Normal "X <= (others => '0')" should be translated properly when X is bit vector Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8285 Retrascope Bug Closed Normal 0% coverage of EFSM transitions for b01 example Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8289 Retrascope Bug Closed Normal ITC99 b02: no resetting transition has been found Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8573 Fortress Bug Closed Normal missing javadoc Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
8681 Retrascope Bug Closed Normal EngineRegistry fails to create toolchain when HashSet\HashMap are used Sergey Smolov Alexander Kamkin Retrascope - 1.0 Actions
8738 Verilog Translator Bug Closed Normal DataMemTestCase falls with error Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8779 Verilog Translator Bug Closed Normal mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8831 Verilog Translator Bug Closed Normal vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8832 Verilog Translator Bug Closed Normal verilog/opencores/mips16/IF_stage.v: java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8846 Verilog Translator Bug Closed Normal test_19_04_00_3.v: Module 'real_last' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8848 Verilog Translator Bug Closed Normal test_07_08_00_1.v: Module 'pullup' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8850 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8851 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8852 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8855 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8856 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_04_05_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8857 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8859 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_3: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8860 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8861 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_03_1: java.lang.IllegalStateException: BigInteger data is not convertible to Boolean. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8862 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_08_02_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8863 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_02_04_4_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8864 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8865 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8912 Retrascope Bug Closed Normal file ram.smv: line 332: variable is assigned more than once: m_ram.mem0 Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8957 Verilog Translator Bug Closed High wrong datatype for arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8991 Retrascope Bug Closed Normal CfgSwitchSequenceBackend: do not collapse "if" statements with incompatible conditions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9010 Retrascope Test Suite Bug Closed Normal Texas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9063 MicroTESK Bug Closed Normal microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMap.java uses unchecked or unsafe operations Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9066 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9071 Retrascope Test Suite Bug Open Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.IllegalArgumentException: Unknown operation 'FUNCTION' Sergey Smolov Mikhail Lebedev Actions
9075 Retrascope Bug Closed Normal java.lang.IllegalArgumentException: testNum 0 != 1 topModuleNum Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9172 Retrascope Test Suite Bug Closed Normal Texas97ParsepackCfgGraphMlTestCase: ru.ispras.retrascope.basis.exception.RetrascopeException: Wrong range: 0 < 0 or 7 > 1. Sergey Smolov Sergey Smolov Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9175 Retrascope Test Suite Bug Closed Normal Texas97PdlxCfgGraphMlTestCase: NullPointerException Sergey Smolov Sergey Smolov Actions
9176 Retrascope Test Suite Bug Closed Normal VcegarHlddSmvPrinterTestCase: java.lang.IllegalArgumentException: Unknown operation 'BVSDIV' Sergey Smolov Mikhail Lebedev Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9184 Veritool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9203 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.basis.HlddAssertSmvTestbenchBenchmarkTest.runTest: java.lang.IllegalArgumentException: 'benchmarks' field is not initialized. Sergey Smolov Mikhail Lebedev Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
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