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# Project Tracker Status Priority Subject Author Assignee Target version
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7733 Trace Matcher Task Closed Normal run.bat script for Windows Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
5904 Retrascope Task Closed Normal save jUnit test results in build/test-results Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5547 Retrascope IDE Bug New Normal save Retrascope result not to ECLIPSE_HOME folder Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9249 Retrascope Task Closed Normal separate jUnit test cases for EfsmGraphMlPrinter engine Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8194 Retrascope Task Closed Normal Separately solve independent sub-expressions of common AND expression Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5399 Fortress Task Closed Normal silent & debug mode Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
6059 Retrascope Task Closed Normal Simple solver for "x && !x" constraints Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
3716 С++TESK Development Environment Task Closed Normal Simple XML dumping\parsing test Sergey Smolov asd ert Actions
8433 Trace Matcher Feature Closed Normal "--skip-equal" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4713 Fortress Task New High SMT-LIB structures Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
6447 Retrascope Task Closed Normal SMV-based counterexamples parser Sergey Smolov Mikhail Lebedev Retrascope - 0.2 Actions
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