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# Project Tracker Status Priority Subject Author Assignee Target version
7081 Retrascope Task Rejected Normal xor-composition-printer Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6412 Retrascope Task Rejected Normal engine combining HLDD & assertion model Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5609 Retrascope Task Rejected Normal make process-local variables be efsm-model-global Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5692 Retrascope Bug Rejected Normal FATE/FATE+ hangs on b03 with Java 1.8 Sergey Smolov Igor Melnichenko Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
5507 Retrascope Task Rejected Normal [engine][basis] implement PrinterEngine Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5320 Retrascope Task Rejected Normal [cfg] Методы копирования вершин CFG Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5004 Retrascope Bug Rejected Normal [efsm][simulator][execution] ReferenceEfsmTestGeneratorTest.java : java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5684 Retrascope Bug Rejected Low computeExpression -> LOGIC_BOOLEAN vs (MAP LOGIC_INTEGER LOGIC_BOOLEAN) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6989 Retrascope IDE Task Rejected Normal migrate to Eclipse Mars (4.5) Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
5127 Retrascope IDE Task Rejected Normal [cfg][printer][graphml] Интегрировать плагин для yEd Sergey Smolov Alexander Protsenko Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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