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# Project Tracker Status Priority Subject Author Assignee Target version
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7474 Verilog Translator Bug Closed Normal missing empty branches for 'if' statements Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8205 Verilog Translator Task Closed Normal Gradle-based build environment Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10382 Verilog Translator Bug Resolved Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug Resolved Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
3654 С++TESK Development Environment Task Closed High source code refactoring Sergey Smolov Sergey Smolov Actions
2224 С++TESK Development Environment Task Closed Normal Добавить пункт со сведениями о плагине Sergey Smolov Alexander Kamkin Actions
3716 С++TESK Development Environment Task Closed Normal Simple XML dumping\parsing test Sergey Smolov asd ert Actions
3717 С++TESK Development Environment Bug Closed Normal Переименовать com.unitesk.cpptesk.ide.prototype.presentations в com.unitesk.cpptesk.ide.prototype.ir Sergey Smolov Sergey Smolov Actions
3623 С++TESK Development Environment Task Closed Normal Внутреннее представление для прототипов тестовых систем Sergey Smolov Sergey Smolov Actions
3624 С++TESK Development Environment Task Closed Normal XML dumping\parsing Sergey Smolov Sergey Smolov Actions
3754 С++TESK Development Environment Task Closed Normal флаг incomparable в полях сообщений Sergey Smolov Sergey Smolov Actions
3757 С++TESK Development Environment Bug Closed Normal Добавить jar-ник SWT в проект com.unitesk.cpptesk.ide.mapper Sergey Smolov Sergey Smolov Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
3759 С++TESK Development Environment Task Feedback Normal Разработать демонстрационный пример для структуры соответствия Sergey Smolov Actions
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