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# Project Tracker Status Priority Subject Author Assignee Target version
8859 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_3: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000_lut: ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8850 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8846 Verilog Translator Bug Closed Normal test_19_04_00_3.v: Module 'real_last' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Verified Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Verified Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8857 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8779 Verilog Translator Bug Closed Normal mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5455 Verilog Translator Task Closed Normal устранить зависимость от ANTLRWorks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8738 Verilog Translator Bug Closed Normal DataMemTestCase falls with error Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8848 Verilog Translator Bug Closed Normal test_07_08_00_1.v: Module 'pullup' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10141 Verilog Translator Bug Verified Normal check port redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9899 Verilog Translator Task Verified Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
10202 Verilog Translator Bug Resolved Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9208 Verilog Translator Task Closed Normal add Verilog2Smv\VIS benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10382 Verilog Translator Bug Resolved Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8205 Verilog Translator Task Closed Normal Gradle-based build environment Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9206 Verilog Translator Task Closed Normal add Texas97 benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug Resolved Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7474 Verilog Translator Bug Closed Normal missing empty branches for 'if' statements Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
2224 С++TESK Development Environment Task Closed Normal Добавить пункт со сведениями о плагине Sergey Smolov Alexander Kamkin Actions
3716 С++TESK Development Environment Task Closed Normal Simple XML dumping\parsing test Sergey Smolov asd ert Actions
3757 С++TESK Development Environment Bug Closed Normal Добавить jar-ник SWT в проект com.unitesk.cpptesk.ide.mapper Sergey Smolov Sergey Smolov Actions
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