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# Project Tracker Status Priority Subject Author Assignee Target version
10044 MicroTESK Bug Resolved Normal Translator crashes with NPE if no instruction is defined Alexander Kamkin Artem Kotsynyak MicroTESK - 2.5 Actions
10040 MicroTESK Bug New Normal Disable checking redeclaration for arguments Alexander Kamkin Artem Kotsynyak MicroTESK - 2.5 Actions
9978 MicroTESK for RISC-V Task New Normal Some templates use rand(-2147483648, 2147483647) for randomizing words Alexander Kamkin Alexander Kamkin MicroTESK for RISC-V - 0.1 Actions
9910 MicroTESK Bug Resolved Normal Symbolic executor fails to construct CFG Alexander Kamkin Artem Kotsynyak MicroTESK - 2.4 Actions
9907 Deductive Verification Tool for Machine Code Task New Normal Проверка инструмента на примерах из MicroTESK for RISC-V Alexander Kamkin Pavel Putro Actions
9846 Aspectrace Task New Normal Source code formatting and improvement Alexander Kamkin Ivan Grigorov Actions
9390 MicroTESK Bug Closed Normal Bug in code allocation Alexander Kamkin Alexander Kamkin MicroTESK - 2.4 Actions
9338 MicroTESK Task Closed Normal Instruction decoding hints Alexander Kamkin Alexander Kamkin MicroTESK - 2.4 Actions
9336 MicroTESK Bug Closed Normal MicroTESK is not able to disassemble euclid binary (RISC-V) Alexander Kamkin Alexander Kamkin MicroTESK - 2.4 Actions
9314 MicroTESK Bug Closed Normal Undesired behavior of situation('random', :size => 32, :sign_extend => true) Alexander Kamkin Alexander Kamkin MicroTESK - 2.4 Actions
9262 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_09_06_00_1: Descriptor has not been found Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9261 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPAREN Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9260 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_02_02_1_2: StackOverflowError Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9259 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_02_4: Task declaration has not been found Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9258 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_02_1 STANDARD_OUT Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9257 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_01_5: IllegalArgumentException Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9256 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_02_00_1: NullPointerException Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9255 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_14_06_04_2_3: no viable alternative Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9254 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_08_00_1: no viable alternative Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9253 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: no viable alternative Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9252 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_01_05_2: Cannot convert a real to a bitvector Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
9229 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_03_05_01_3: incorrect token under disabled if-def Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
8833 Verilog Translator Bug Closed Normal Error when building AST for if-generate constructs without else branches Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
8818 Verilog Translator Feature Closed Normal Extending grammar to allow else if Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
8804 Verilog Translator Bug Closed Normal Exception when dividing 4-bit vector by 32-bit one Alexander Kamkin Alexander Kamkin Verilog Translator - 0.1 Actions
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