Verilog Translator

Suppose there are two files with Verilog modules: a.v and b.v (a.v contains "a" module, b.v contains "b" module). Module "a" includes module "b".

When the following args are used for the tool:

a.v b.v --include-path /path/to/b/file --module-name a

the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.
More adequate diagnostics should be shown here, and, of course, no freezes.