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Feature #9990

closed

check for variable/net redeclarations

Added by Sergey Smolov about 3 years ago. Updated over 2 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexey Danilov
Target version:
0.1
Start date:
12/17/2019
Due date:
% Done:

50%

Estimated time:
Published in build:
0.1.3-beta-201002

Description

As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,

It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.

So the tool should detect erroneous redeclarations.

For more details see 4.2.1 and 4.2.2 chapters.

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 #1

Updated by Sergey Smolov almost 3 years ago

  • Status changed from New to Feedback
  • Assignee changed from Alexander Kamkin to Alexey Danilov
  • Priority changed from Normal to High

Alexey, could you implement this small feature? It is relevant to your work at VeriTrans.

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 #2

Updated by Alexey Danilov almost 3 years ago

  • Status changed from Feedback to Resolved
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 #3

Updated by Alexey Danilov almost 3 years ago

  • % Done changed from 0 to 50
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 #4

Updated by Alexey Danilov almost 3 years ago

  • Status changed from Resolved to Open
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 #5

Updated by Alexey Danilov almost 3 years ago

  • Status changed from Open to Resolved
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 #6

Updated by Sergey Smolov almost 3 years ago

  • Status changed from Resolved to Verified
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 #7

Updated by Sergey Smolov over 2 years ago

  • Status changed from Verified to Closed
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 #8

Updated by Sergey Smolov over 2 years ago

  • Published in build set to 0.1.3-beta-201002
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