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Feature #9990

check for variable/net redeclarations

Added by Sergey Smolov 12 months ago. Updated about 2 months ago.

Status:
Closed
Priority:
High
Target version:
Start date:
12/17/2019
Due date:
% Done:

50%

Estimated time:
Published in build:
0.1.3-beta-201002

Description

As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,

It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.

So the tool should detect erroneous redeclarations.

For more details see 4.2.1 and 4.2.2 chapters.

History

#1

Updated by Sergey Smolov 9 months ago

  • Priority changed from Normal to High
  • Assignee changed from Alexander Kamkin to Alexey Danilov
  • Status changed from New to Feedback

Alexey, could you implement this small feature? It is relevant to your work at VeriTrans.

#2

Updated by Alexey Danilov 9 months ago

  • Status changed from Feedback to Resolved
#3

Updated by Alexey Danilov 9 months ago

  • % Done changed from 0 to 50
#4

Updated by Alexey Danilov 9 months ago

  • Status changed from Resolved to Open
#5

Updated by Alexey Danilov 8 months ago

  • Status changed from Open to Resolved
#6

Updated by Sergey Smolov 7 months ago

  • Status changed from Resolved to Verified
#7

Updated by Sergey Smolov about 2 months ago

  • Status changed from Verified to Closed
#8

Updated by Sergey Smolov about 2 months ago

  • Published in build set to 0.1.3-beta-201002

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