Feature #9990
check for variable/net redeclarations
Start date:
12/17/2019
Due date:
% Done:
50%
Estimated time:
Published in build:
0.1.3-beta-201002
Description
As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,
It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
So the tool should detect erroneous redeclarations.
For more details see 4.2.1 and 4.2.2 chapters.
History
Updated by Sergey Smolov about 1 year ago
Updated by - Priority changed from Normal to High
- Assignee changed from Alexander Kamkin to Alexey Danilov
- Status changed from New to Feedback
Alexey, could you implement this small feature? It is relevant to your work at VeriTrans.
Updated by