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Feature #9990

check for variable/net redeclarations

Added by Sergey Smolov 2 months ago.

Status:
New
Priority:
Normal
Target version:
Start date:
12/17/2019
Due date:
% Done:

0%

Estimated time:
Published in build:

Description

As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,

It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.

So the tool should detect erroneous redeclarations.

For more details see 4.2.1 and 4.2.2 chapters.

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