check for variable/net redeclarations
Published in build:
As it is specified in IEEE-1364-2005 Standard for Verilog Hardware Description Language,
It is illegal to redeclare a name already declared by a net, parameter, or variable declaration.
So the tool should detect erroneous redeclarations.
For more details see 4.2.1 and 4.2.2 chapters.
- Priority changed from Normal to High
- Assignee changed from Alexander Kamkin to Alexey Danilov
- Status changed from New to Feedback
Alexey, could you implement this small feature? It is relevant to your work at VeriTrans.
- Status changed from Feedback to Resolved
- % Done changed from 0 to 50
- Status changed from Resolved to Open
- Status changed from Open to Resolved
- Status changed from Resolved to Verified
- Status changed from Verified to Closed
- Published in build set to 0.1.3-beta-201002
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