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Bug #9915

closed

"Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file

Added by Sergey Smolov about 5 years ago. Updated about 4 years ago.

Status:
Closed
Priority:
Urgent
Assignee:
Alexey Danilov
Target version:
0.1
Start date:
11/13/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.3-beta-201002

Description

The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.

To reproduce the bug, checkout to 5ca788cd commit and run ru.ispras.verilog.parser.VerilogQuipTestCase. It should be fail-free, but it is not.

IMPORTANT: please run all the project tests before push and compare your results with Jenkins!

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 #1

Updated by Sergey Smolov about 5 years ago

IMPORTANT №2: run "./gradlew checkStyle" command in your repo and fix coding style issues in your classes before push too!

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 #2

Updated by Alexey Danilov almost 5 years ago

  • Status changed from New to Resolved
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 #3

Updated by Sergey Smolov almost 5 years ago

  • Status changed from Resolved to Verified
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 #4

Updated by Sergey Smolov about 4 years ago

  • Status changed from Verified to Closed
  • Published in build set to 0.1.3-beta-201002
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