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Bug #9915

"Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file

Added by Sergey Smolov 8 months ago. Updated 7 months ago.

Status:
Verified
Priority:
Urgent
Target version:
Start date:
11/13/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.

To reproduce the bug, checkout to 5ca788cd commit and run ru.ispras.verilog.parser.VerilogQuipTestCase. It should be fail-free, but it is not.

IMPORTANT: please run all the project tests before push and compare your results with Jenkins!

History

#1

Updated by Sergey Smolov 8 months ago

IMPORTANT №2: run "./gradlew checkStyle" command in your repo and fix coding style issues in your classes before push too!

#2

Updated by Alexey Danilov 7 months ago

  • Status changed from New to Resolved
#3

Updated by Sergey Smolov 7 months ago

  • Status changed from Resolved to Verified

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