"Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file
The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.
To reproduce the bug, checkout to 5ca788cd commit and run ru.ispras.verilog.parser.VerilogQuipTestCase. It should be fail-free, but it is not.
IMPORTANT: please run all the project tests before push and compare your results with Jenkins!