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Task #9899

closed

VerilogPrinter test cases for QUIP benchmarks

Added by Sergey Smolov about 5 years ago. Updated about 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Maxim Chudnov
Target version:
0.1
Start date:
10/31/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Published in build:
0.1.3-beta-201002
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 #1

Updated by Sergey Smolov about 5 years ago

  • Project changed from Retrascope Test Suite to Verilog Translator
  • Category deleted (Verilog Translator)
  • Target version set to 0.1
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 #2

Updated by Maxim Chudnov about 5 years ago

  • Status changed from New to Resolved
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 #3

Updated by Sergey Smolov about 5 years ago

  • Status changed from Resolved to Verified
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 #4

Updated by Sergey Smolov about 4 years ago

  • Status changed from Verified to Closed
  • Published in build set to 0.1.3-beta-201002
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