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Task #9811

macro with parameters

Added by Sergey Smolov 10 months ago. Updated 3 months ago.

Status:
Verified
Priority:
High
Assignee:
Alexey Danilov
Target version:
0.2
Start date:
09/05/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Published in build:

Description

Macro with parameters are used, for example, in RISC-V cores like picorv32 (see Retrascope for RISC-V).

Related issues

Related to Retrascope RISC-V Benchmark - Bug #9475: Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '('Closed02/06/2019

Actions
Related to Verilog Translator - Bug #9261: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPARENVerified08/31/2018

Actions

History

#1

Updated by Sergey Smolov 10 months ago

  • Related to Bug #9475: Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' added
#2

Updated by Sergey Smolov 10 months ago

  • Related to Bug #9261: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPAREN added
#3

Updated by Sergey Smolov 8 months ago

  • Priority changed from Normal to High
#4

Updated by Alexander Kamkin 8 months ago

  • Assignee changed from Alexander Kamkin to Alexey Danilov
#5

Updated by Alexey Danilov 7 months ago

  • Status changed from New to Resolved
#6

Updated by Sergey Smolov 3 months ago

  • Status changed from Resolved to Verified

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