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Task #9811

macro with parameters

Added by Sergey Smolov about 1 year ago. Updated about 2 months ago.

Status:
Closed
Priority:
High
Target version:
Start date:
09/05/2019
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Published in build:
0.1.3-beta-201002

Description

Macro with parameters are used, for example, in RISC-V cores like picorv32 (see Retrascope for RISC-V).


Related issues

Related to Retrascope RISC-V Benchmark - Bug #9475: Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '('Closed02/06/2019

Actions
Related to Verilog Translator - Bug #9261: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPARENClosed08/31/2018

Actions

History

#1

Updated by Sergey Smolov about 1 year ago

  • Related to Bug #9475: Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' added
#2

Updated by Sergey Smolov about 1 year ago

  • Related to Bug #9261: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPAREN added
#3

Updated by Sergey Smolov about 1 year ago

  • Priority changed from Normal to High
#4

Updated by Alexander Kamkin about 1 year ago

  • Assignee changed from Alexander Kamkin to Alexey Danilov
#5

Updated by Alexey Danilov 12 months ago

  • Status changed from New to Resolved
#6

Updated by Sergey Smolov 7 months ago

  • Status changed from Resolved to Verified
#7

Updated by Sergey Smolov about 2 months ago

  • Published in build set to 0.1.3-beta-201002
  • Status changed from Verified to Closed

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