Verilog Translator

For the following module:

module bv_non_zero_idx(in, clk, out);
  input [2:1]  in;
  input        clk;
  output [1:0] out;

  reg [1:0] data;

  assign out = data;

  always @(posedge clk)
    begin
      if (in[2:2] == 1'b1)
        begin
          data <= 2'b11;
        end
      if (in[1:1] == 1'b0)
        begin
          data <= 2'b01;
        end
    end
endmodule

the VerilogPrinter engine produces the following output:

module bv_non_zero_idx(in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */, in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */);
  input [00000000000000000000000000000010 /* 00000000000000000000000000000010 */:00000000000000000000000000000001 /* 00000000000000000000000000000001 */] in;
  input clk;
  output [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] out;
  reg [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] data;
  assign out /* DECL: out */ = data /* data */;
  always
    @(posedge clk /* clk */)
      begin: block.0
        if((in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */)
          /* ASSERT: (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */ */
          begin: block.1
             data /* DECL: data */ <= 11 /* 11 */;
          end
        else
          /* ASSERT:  ! (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1)) */ */
          begin: block.2
          end
        end
        if((in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */)
          /* ASSERT: (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */ */
          begin: block.3
             data /* DECL: data */ <= 01 /* 01 */;
          end
        else
          /* ASSERT:  ! (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0)) */ */
          begin: block.4
          end
        end
      end
endmodule

WARN: Can't cast (BVEXTRACT 2 2 in) to (BIT_VECTOR 1) type; no changes.
@(posedge clk)
  begin: block.0
    if((in[2:2] == 1))
      begin: block.1
         bv_non_zero_idx.data <= 11;
      end
    else
      begin: block.2
      end
    end
    if((in[1:1] == 0))
      begin: block.3
         bv_non_zero_idx.data <= 01;
      end
    else
      begin: block.4
      end
    end
  end
assign out = bv_non_zero_idx.data;

Here params for BVEXTRACT operation of in variable are incorrect: an offset should be taken into account