Feature #9774: Case expression/value type casting - Verilog Translator - Open-Source Projects

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Feature #9774

closed

Case expression/value type casting

Added by Mikhail Lebedev over 5 years ago. Updated about 5 years ago.

Status:

Closed

Priority:

High

Assignee:

Sergey Smolov

Target version:

0.1

Start date:

07/26/2019

Due date:

% Done:

100%

Estimated time:

Published in build:

0.1.2-beta-190909

Description

There can be a situation when an expression in a case and its possible values have different types. For example, vcegar/zaher/zdlx_impl.v_for_pred.v :

...
wire [7:0] concat_rep50_3;
...
wire [7:0] concat_rep50_4;
...
case (ID_EX_EXCTRL[4:3])
  concat_rep50_3:
    ALUCtrl =  3'b010;
  concat_rep50_4:
    ALUCtrl =  0;
endcase

This situation may lead to an incompatible types error in some tools. Type casting should be performed.