Verilog Translator

There can be a situation when an expression in a case and its possible values have different types. For example, vcegar/zaher/zdlx_impl.v_for_pred.v :

...
wire [7:0] concat_rep50_3;
...
wire [7:0] concat_rep50_4;
...
case (ID_EX_EXCTRL[4:3])
  concat_rep50_3:
    ALUCtrl =  3'b010;
  concat_rep50_4:
    ALUCtrl =  0;
endcase

This situation may lead to an incompatible types error in some tools. Type casting should be performed.