Project

General

Profile

Actions
Copy link

Task #9726

closed

VerilogPrinter test cases

Added by Sergey Smolov almost 5 years ago. Updated almost 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Verilog Translator
Start date:
07/02/2019
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:

Description

Add test cases for VerilogPrinter component of Verilog Translator tool for the following benchmarks: Texas-97, VCEGAR, Verilog2SMV

Actions
Copy link

Also available in: Atom PDF