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Task #9726
closedVerilogPrinter test cases
Start date:
07/02/2019
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Published in build:
Description
Add test cases for VerilogPrinter component of Verilog Translator tool for the following benchmarks: Texas-97, VCEGAR, Verilog2SMV
Updated by Sergey Smolov almost 5 years ago
- Status changed from New to Open
- Detected in build changed from svn to master
Updated by Sergey Smolov almost 5 years ago
- Status changed from Open to Resolved
- % Done changed from 0 to 100
Test cases are implemented in ru.ispras.verilog.parser.sample package.
Updated by Sergey Smolov almost 5 years ago
- Status changed from Resolved to Closed
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