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Task #9726

VerilogPrinter test cases

Added by Sergey Smolov 13 days ago. Updated 13 days ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Verilog Translator
Start date:
07/02/2019
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:

Description

Add test cases for VerilogPrinter component of Verilog Translator tool for the following benchmarks: Texas-97, VCEGAR, Verilog2SMV

History

#1

Updated by Sergey Smolov 13 days ago

  • Detected in build changed from svn to master
  • Status changed from New to Open
#2

Updated by Sergey Smolov 13 days ago

  • % Done changed from 0 to 100
  • Status changed from Open to Resolved

Test cases are implemented in ru.ispras.verilog.parser.sample package.

#3

Updated by Sergey Smolov 13 days ago

  • Status changed from Resolved to Closed

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