Verilog Translator

According to the Verilog 2005 standard, net declaration assignment is a form of a continuous assignment. Veritrans handles it as an initial value assignment, not as a process.

Chapter 6.1.1 of the standard:

... the net declaration assignment, allows a continuous assignment to be placed on a net in the same statement that declares the net.

The following is an example of the net declaration form of a continuous assignment:

wire (strong1, pull0) mynet = enable ;
...

See test_06_01_01_1.