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Bug #9514

Net declaration assignment is a continuous assignment

Added by Mikhail Lebedev over 1 year ago. Updated about 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
Target version:
Start date:
03/01/2019
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.2-beta-190909

Description

According to the Verilog 2005 standard, net declaration assignment is a form of a continuous assignment. Veritrans handles it as an initial value assignment, not as a process.

Chapter 6.1.1 of the standard:

... the net declaration assignment, allows a continuous assignment to be placed on a net in the same statement that declares the net.

The following is an example of the net declaration form of a continuous assignment:

wire (strong1, pull0) mynet = enable ;
...

See test_06_01_01_1.

History

#1

Updated by Sergey Smolov about 1 year ago

  • Detected in build changed from svn to master
  • % Done changed from 0 to 100
  • Assignee changed from Alexander Kamkin to Sergey Smolov
  • Status changed from New to Resolved

Done in 7fc1232d

#2

Updated by Mikhail Lebedev about 1 year ago

  • Status changed from Resolved to Verified
#3

Updated by Sergey Smolov about 1 year ago

  • Published in build set to 0.1.2-beta-190909
  • Target version set to 0.1
  • Status changed from Verified to Closed

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