Bug #9478
open
ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int'
Added by Sergey Smolov over 5 years ago.
Updated about 4 years ago.
Category:
Verilog Translator
Description
The ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase test case falls with the following error:
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:6 mismatched input 'unsigned' expecting LPAREN
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 31:4 missing KW_BEGIN at 'void'
ERROR: [Internal] null
The related Verilog code is as follows:
int unsigned rand_value;
The problematic code is a SystemVerilog code.
- Subject changed from ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPAREN to ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int'
- Assignee changed from Alexander Kamkin to Mikhail Lebedev
ERROR: D:\Bot\projects\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int'
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <unexpected: [@107,608:610='int',<106>,28:2], resync=moduleTestDriver;regclock=1'b0;regreset=1'b1;always#(1.0/2.0)clock=~clock;initial#(777.7)reset=0;regverbose=1'b0;wireprintf_cond=verbose&&!reset;reg[63:0]max_cycles=0;reg[63:0]dump_start=0;reg[63:0]trace_count=0;reg[1023:0]fsdbfile=0;reg[1023:0]vcdplusfile=0;reg[1023:0]vcdfile=0;intunsignedrand_value;initialbeginvoid'> expecting AST_MODULE_ITEMS
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <unexpected: [@115,660:660='(',<221>,31:9], resync=(> expecting <UP>
module null();
endmodule
ERROR: Module 'TestDriver' has not been found
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:54)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:234)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogPrinterTest.runTest(VerilogPrinterTest.java:49)
- Assignee deleted (
Mikhail Lebedev)
SystemVerilog should be supported by Verilog Translator
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