Retrascope » Retrascope RISC-V Benchmark

The ru.ispras.verilog.parser.sample.RocketChipSimJtagVerilogPrinterTestCase test case runs Verilog Translator on SimJTAG.v module, that contains the following code:

import "DPI-C" function int jtag_tick
(
 output bit jtag_TCK,
 output bit jtag_TMS,
 output bit jtag_TDI,
 output bit jtag_TRSTn,

 input bit  jtag_TDO
);

module SimJTAG #(
                 parameter TICK_DELAY = 50
                 )(

                   input         clock,
                   input         reset,
...

The "import function" construction causes the following error:

ERROR: ..\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\SimJTAG.v line 3:0 mismatched input 'import' expecting EOF
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@0,71:76='import',<35>,3:0], resync=import"DPI-C"functionintjtag_tick(outputbitjtag_TCK,outputbitjtag_TMS,outputbitjtag_TDI,outputbitjtag_TRSTn,inputbitjtag_TDO);moduleSimJTAG#(parameterTICK_DELAY=50)(inputclock,inputreset,inputenable,inputinit_done,outputjtag_TCK,outputjtag_TMS,outputjtag_TDI,outputjtag_TRSTn,inputjtag_TDO_data,inputjtag_TDO_driven,output[31:0]exit);reg[31:0]tickCounterReg;wire[31:0]tickCounterNxt;assigntickCounterNxt=(tickCounterReg==0)?TICK_DELAY:(tickCounterReg-1);bitr_reset;wire[31:0]random_bits=$random;wire#0.1__jtag_TDO=jtag_TDO_driven?jtag_TDO_data:random_bits[0];bit__jtag_TCK;bit__jtag_TMS;bit__jtag_TDI;bit__jtag_TRSTn;int__exit;reginit_done_sticky;assign#0.1jtag_TCK=__jtag_TCK;assign#0.1jtag_TMS=__jtag_TMS;assign#0.1jtag_TDI=__jtag_TDI;assign#0.1jtag_TRSTn=__jtag_TRSTn;assign#0.1exit=__exit;always@(posedgeclock)beginr_reset<=reset;if(reset||r_reset)begin__exit=0;tickCounterReg<=TICK_DELAY;init_done_sticky<=1'b0;__jtag_TCK=!__jtag_TCK;endelsebegininit_done_sticky<=init_done|init_done_sticky;if(enable&&init_done_sticky)begintickCounterReg<=tickCounterNxt;if(tickCounterReg==0)begin__exit=jtag_tick(__jtag_TCK,__jtag_TMS,__jtag_TDI,__jtag_TRSTn,__jtag_TDO);endendendendendmodule> expecting AST_ROOT
ERROR: Module 'SimJTAG' has not been found

The same error appears at the following test cases:
ru.ispras.verilog.parser.sample.RocketChipSimDtmVerilogPrinterTestCase