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Feature #9468
closedHDL parser backend that removes 'initial' processes
Start date:
01/31/2019
Due date:
% Done:
100%
Estimated time:
Published in build:
1.1.1-beta-190722
Description
In Verilog, 'initial' blocks are non-synthesizable, as 2005 standard tells.
The backend for HDL parser should be implemented that removes such processes from CFG.
When the 'initial' block contains variables' initialization assignments, these values (if constants!) should be stored at the variables' declarations.
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