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Bug #9296

vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean

Added by Sergey Smolov over 1 year ago. Updated 6 months ago.

Status:
Closed
Priority:
High
Target version:
Start date:
10/04/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.1-beta-190722

Description

The 46th line of two_processor_bin_2.v file:

assign ND_inB = (master_outA ) ? ND_inA : (ndB && !bus_ackB);

produces the error via model checking:
illegal types of "then" and "else" expressions : unsigned word[1] and boolean

The ND_inA variable has 1-bit vector dataType ("then"), but the "ndB && !bus_ackB" expression ("else") is represented by the VeriTrans as follows: (AND (EQ bus_ackB 0) (NOT (EQ ndB 0))).
So it has Boolean data type since all operations are logic, not bitvector-oriented.

History

#1

Updated by Sergey Smolov 6 months ago

  • Published in build set to 0.1.1-beta-190722
  • % Done changed from 0 to 100
  • Status changed from New to Closed

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