vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word and boolean
Detected in build:
Published in build:
The 46th line of two_processor_bin_2.v file:
assign ND_inB = (master_outA ) ? ND_inA : (ndB && !bus_ackB);
produces the error via model checking:
illegal types of "then" and "else" expressions : unsigned word and boolean
The ND_inA variable has 1-bit vector dataType ("then"), but the "ndB && !bus_ackB" expression ("else") is represented by the VeriTrans as follows: (AND (EQ bus_ackB 0) (NOT (EQ ndB 0))).
So it has Boolean data type since all operations are logic, not bitvector-oriented.