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Bug #9282

closed

ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
High
Target version:
Start date:
09/15/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

In the ru.ispras.verilog.parser.sample.DataMemTestCase log the following record appears:

DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)

It comes from the following fragment of the Verilog '_data_mem.v_' module:
wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];

The Fortress node that is created from the right hand side expression of this assignment is incorrect, because the first param of BVEXTRACT operation should be greater or equal to the second one.

Actions #1

Updated by Sergey Smolov over 5 years ago

  • Subject changed from Dru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) to ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)
Actions #2

Updated by Alexander Kamkin over 5 years ago

  • Status changed from New to Resolved
Actions #3

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Verified
Actions #4

Updated by Sergey Smolov over 5 years ago

  • Status changed from Verified to Closed
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