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Bug #9282

ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)

Added by Sergey Smolov about 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
High
Target version:
Start date:
09/15/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

In the ru.ispras.verilog.parser.sample.DataMemTestCase log the following record appears:

DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)

It comes from the following fragment of the Verilog '_data_mem.v_' module:
wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];

The Fortress node that is created from the right hand side expression of this assignment is incorrect, because the first param of BVEXTRACT operation should be greater or equal to the second one.

History

#1

Updated by Sergey Smolov about 2 years ago

  • Subject changed from Dru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) to ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)
#2

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from New to Resolved
#3

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Resolved to Verified
#4

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Verified to Closed

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