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Task #9263

SystemVerilog Assertions support in Verilog Translator

Added by Mikhail Lebedev over 1 year ago. Updated about 2 months ago.

Status:
New
Priority:
Normal
Target version:
Start date:
12/03/2019
Due date:
% Done:

0%

Estimated time:
(Total: 0.00 h)
Detected in build:
svn
Published in build:

Description

SystemVerilog assertions (SVA) and properties support is needed in Verilog Translator. This task includes the following sub-tasks:
1) SVA syntax support.
2) Variable renaming in properties during elaboration.


Subtasks

Task #9961: uncomment jUnit test cases that are related to SVA modulesNewSergey Smolov

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Related issues

Related to Retrascope RISC-V Benchmark - Bug #9478: ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPARENNew02/06/2019

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History

#1

Updated by Alexander Kamkin over 1 year ago

  • Target version set to 0.2
#2

Updated by Sergey Smolov 7 months ago

  • Assignee changed from Alexander Kamkin to Mikhail Lebedev
#3

Updated by Sergey Smolov 5 months ago

  • Related to Bug #9478: ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPAREN added
#4

Updated by Sergey Smolov 3 months ago

  • Priority changed from Normal to High

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