Project

General

Profile

Task #9263

SystemVerilog Assertions support in Verilog Translator

Added by Mikhail Lebedev about 1 year ago. Updated 19 days ago.

Status:
New
Priority:
High
Target version:
Start date:
09/03/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Published in build:

Description

SystemVerilog assertions (SVA) and properties support is needed in Verilog Translator. This task includes the following sub-tasks:
1) SVA syntax support.
2) Variable renaming in properties during elaboration.


Related issues

Related to Retrascope RISC-V Benchmark - Bug #9478: ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPARENNew02/06/2019

Actions

History

#1

Updated by Alexander Kamkin about 1 year ago

  • Target version set to 0.2
#2

Updated by Sergey Smolov 5 months ago

  • Assignee changed from Alexander Kamkin to Mikhail Lebedev
#3

Updated by Sergey Smolov 3 months ago

  • Related to Bug #9478: ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPAREN added
#4

Updated by Sergey Smolov 19 days ago

  • Priority changed from Normal to High

Also available in: Atom PDF