Verilog Translator

    ERROR: line 1:0 no viable alternative at input '('
    ERROR: line 1:4 mismatched input ')' expecting LPAREN
    ERROR: C:\SVN\veritrans\src\test\verilog\ieee-tests\test_19_03_01_1.v line 29:15 missing SEMI at 'g121'
    ERROR: line 1:0 no viable alternative at input '('
    ERROR: line 1:4 mismatched input ')' expecting LPAREN
    ERROR: C:\SVN\veritrans\src\test\verilog\ieee-tests\test_19_03_01_1.v line 30:15 missing SEMI at 'g122'
    ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 1:0 mismatched tree node: <unexpected: [@11,0:0='(',<160>,1:0], resync=(> expecting <UP>
    ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 1:1 mismatched tree node: AST_STRENGTH expecting <UP>