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Bug #9261

ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPAREN

Added by Alexander Kamkin about 1 year ago. Updated about 1 year ago.

Status:
New
Priority:
Normal
Target version:
Start date:
08/31/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

    ERROR: line 1:0 no viable alternative at input '('
    ERROR: line 1:4 mismatched input ')' expecting LPAREN
    ERROR: C:\SVN\veritrans\src\test\verilog\ieee-tests\test_19_03_01_1.v line 29:15 missing SEMI at 'g121'
    ERROR: line 1:0 no viable alternative at input '('
    ERROR: line 1:4 mismatched input ')' expecting LPAREN
    ERROR: C:\SVN\veritrans\src\test\verilog\ieee-tests\test_19_03_01_1.v line 30:15 missing SEMI at 'g122'
    ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 1:0 mismatched tree node: <unexpected: [@11,0:0='(',<160>,1:0], resync=(> expecting <UP>
    ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 1:1 mismatched tree node: AST_STRENGTH expecting <UP>

Related issues

Related to Verilog Translator - Task #9811: macro with parametersNew09/05/2019

Actions

History

#1

Updated by Alexander Kamkin about 1 year ago

Defines with parameters.

#2

Updated by Sergey Smolov 18 days ago

  • Related to Task #9811: macro with parameters added

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