Bug #9255: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_14_06_04_2_3: no viable alternative - Verilog Translator - Open-Source Projects

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Bug #9255

closed

ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_14_06_04_2_3: no viable alternative

Added by Alexander Kamkin over 6 years ago. Updated over 6 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Alexander Kamkin

Target version:

0.1

Start date:

08/31/2018

Due date:

% Done:

Estimated time:

Detected in build:

svn

Platform:

Published in build:

Description

module test;
  input a, b;
  output out, out_b;

  specify
    showcancelled out;
    pulsestyle_ondetect out;
    (a => out) = (2,3);
    (b => out) = (4,5);
    showcancelled out_b;
    pulsestyle_ondetect out_b;
    (a => out_b) = (3,4);
    (b => out_b) = (5,6);
  endspecify
  specify
    showcancelled out,out_b;
    pulsestyle_ondetect out,out_b;
    (a => out) = (2,3);
    (b => out) = (4,5);
    (a => out_b) = (3,4);
    (b => out_b) = (5,6);
  endspecify
endmodule