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Bug #9253

ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: no viable alternative

Added by Alexander Kamkin over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Target version:
Start date:
08/31/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
svn
Platform:
Published in build:

Description

module test;
  input in1, in2;
  output out1;
  nor (highz1,strong0) n1(out1,in1,in2);
endmodule

History

#1

Updated by Alexander Kamkin over 1 year ago

  • Subject changed from ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: to ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: no viable alternative
#2

Updated by Alexander Kamkin over 1 year ago

  • Status changed from New to Resolved

Bug fix in the grammar.

#3

Updated by Alexander Kamkin over 1 year ago

  • Status changed from Resolved to Closed

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