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Bug #9252

closed

ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_01_05_2: Cannot convert a real to a bitvector

Added by Alexander Kamkin over 6 years ago. Updated about 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
08/31/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.3-beta-201002

Description

Support for real variables.

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 #1

Updated by Sergey Smolov over 5 years ago

  • Status changed from New to Resolved
  • % Done changed from 0 to 100
  • Detected in build changed from svn to master

Fixed in fd214fb4

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 #2

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Verified

Additinal fix is here: d632d962

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 #3

Updated by Sergey Smolov about 4 years ago

  • Status changed from Verified to Closed
  • Published in build set to 0.1.3-beta-201002
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