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Bug #9250

ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'

Added by Sergey Smolov about 2 years ago. Updated about 1 year ago.

Status:
Closed
Priority:
High
Target version:
Start date:
08/29/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.1-beta-190722

Description

The test produces the following error log:

...
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'

java.lang.StackOverflowError
    at ru.ispras.verilog.parser.grammar.VerilogParser.number(VerilogParser.java)
    at ru.ispras.verilog.parser.grammar.VerilogParser.primary(VerilogParser.java:26555)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_0(VerilogParser.java:23694)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_1(VerilogParser.java:23770)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_2(VerilogParser.java:23865)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_3(VerilogParser.java:23997)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_4(VerilogParser.java:24167)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_5(VerilogParser.java:24333)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_6(VerilogParser.java:24503)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_7(VerilogParser.java:24673)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_8(VerilogParser.java:24843)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_9(VerilogParser.java:25013)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_10(VerilogParser.java:25183)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_11(VerilogParser.java:25353)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_12(VerilogParser.java:25523)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_13(VerilogParser.java:25693)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression_14(VerilogParser.java:25868)
    at ru.ispras.verilog.parser.grammar.VerilogParser.expression(VerilogParser.java:26037)
    at ru.ispras.verilog.parser.grammar.VerilogParser.discrete_assignment_statement(VerilogParser.java:12931)
...

History

#1

Updated by Sergey Smolov about 2 years ago

  • Priority changed from Urgent to High
  • Status changed from New to Open

This bug is caused by 'PC_WIDTH' macro calls inside 'mips16/IF_stage.v' Verilog module. Now these calls are substituted by the macro's true value (8).
The problem will be fixed when moving to ANTLRv4 has been finished.
Temporary fix: 4a211a80

#2

Updated by Sergey Smolov about 1 year ago

  • Published in build set to 0.1.1-beta-190722
  • % Done changed from 0 to 100
  • Status changed from Open to Closed

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