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Bug #9239

closed

ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException

Added by Sergey Smolov over 5 years ago. Updated over 4 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
08/20/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.1-beta-190722

Description

The tool's error log includes the following:

ERROR: ../src/test/verilog/rest-tests/mips16/IF_stage.v line 31:24 extraneous input ''b0' expecting SEMI
DEBUG: Expanding macro '8' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '8' ...
DEBUG: End of the token source 'null'
ERROR: ../src/test/verilog/rest-tests/mips16/IF_stage.v line 39:25 extraneous input ''d1' expecting SEMI

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 #1

Updated by Sergey Smolov over 5 years ago

This error appears in ru.ispras.verilog.parser.sample.IfStageTestCase test case too.

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 #2

Updated by Sergey Smolov over 4 years ago

  • Status changed from New to Closed
  • % Done changed from 0 to 100
  • Published in build set to 0.1.1-beta-190722
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