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2018-08-24T09:30:25Z
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Verilog Translator - Bug #9230: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException
https://forge.ispras.ru/issues/9230?journal_id=34523
2018-08-24T09:30:25Z
Sergey Smolov
smolov@ispras.ru
<ul><li><strong>Status</strong> changed from <i>New</i> to <i>Resolved</i></li><li><strong>Assignee</strong> changed from <i>Alexander Kamkin</i> to <i>Sergey Smolov</i></li><li><strong>% Done</strong> changed from <i>0</i> to <i>100</i></li></ul><p>Fixed in <a class="changeset" title="[jUnit] Texas97: add missing modules to test cases Signed-off-by: Sergey Smolov <smolov@ispras.ru>" href="https://forge.ispras.ru/projects/veritrans/repository/veritrans/revisions/aab9624231adc7d2efcc50b264570358d7208bd8">aab96242</a>, but additional error diagnostics is needed.</p>
Verilog Translator - Bug #9230: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException
https://forge.ispras.ru/issues/9230?journal_id=34526
2018-08-24T09:32:59Z
Sergey Smolov
smolov@ispras.ru
<ul><li><strong>Status</strong> changed from <i>Resolved</i> to <i>Verified</i></li></ul>
Verilog Translator - Bug #9230: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException
https://forge.ispras.ru/issues/9230?journal_id=34527
2018-08-24T09:33:06Z
Sergey Smolov
smolov@ispras.ru
<ul><li><strong>Status</strong> changed from <i>Verified</i> to <i>Closed</i></li></ul>