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Bug #9226
closedru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property'
Start date:
08/16/2018
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Platform:
Published in build:
Description
The code fragment:
always begin
assert property: ((dataOut == tmp_stageTwo + tmp_stageOne) || (dataOut == 0));
end
produces the following error:
ERROR: ../src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 37:8 mismatched tree node: <unexpected: [@152,773:780='property',<31>,38:10], resync=assert> expecting <UP> ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 37:8 mismatched tree node: AST_ATTRIBUTES expecting <UP> ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 37:8 mismatched tree node: UP expecting AST_ATTRIBUTES
The similar error appears in ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_sdlx_control1_smv test case.
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