Verilog Translator

java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH
    at ru.ispras.fortress.expression.NodeOperation.getParams(NodeOperation.java:289)
    at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:197)
    at ru.ispras.fortress.expression.Node.isType(Node.java:177)
    at ru.ispras.fortress.expression.ExprUtils.isType(ExprUtils.java:84)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:216)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:180)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:191)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:210)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignBegin(VerilogTransformer.java:77)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:54)
    at ru.ispras.verilog.parser.elaborator.VerilogCallCollector.transform(VerilogCallCollector.java:55)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.addProcess(VerilogElaborator.java:460)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:324)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:194)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:170)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
    at ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1(VerilogVisVerilog2SmvTestCase.java:121)

This bug comes from the fact, that 'LOGLENGTH' parameter was not substituted by it's value '2'in the resulting representation of the 'twoFifo1.v' Verilog module. The module includes the following code:

/*
*
*    Taken from VIS Benchmarks <ftp://vlsi.colorado.edu/pub/vis/vis-verilog-models-1.3.tar.gz>
*    Modified by Ahmed Irfan <irfan@fbk.eu>
*
*/
module sampleq (reset, inaddr, validin, readin, clkin, bus_gnt_raw,
        outaddr, validout, outisaread, readheadentry);
...
    parameter        LOGLENGTH = 2; //no. of bits required to encode
                                       // head/tail pointers
    reg [LOGLENGTH-1:0]    readtail; // points to the next incoming read address
    reg [LOGLENGTH-1:0]    readhead; // points to the next outgoing read address
    wire        readfull, writefull, readempty, writeempty;
...
    // read queue is full
    assign readfull = (((readtail +1)&{LOGLENGTH{1'b1}}) == readhead);
...
endmodule // sampleq