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Task #9216
closedremove tests for Verilog Translator from project
Start date:
08/12/2018
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Published in build:
Description
Now all the benchmarks (Texas97, VCEGAR, Verilog2SMV/VIS) are added to Verilog Translator project and used there as tests.
In this project we should concentrate on tests for Retrascope.
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