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Task #9216

closed

remove tests for Verilog Translator from project

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Mikhail Lebedev
Category:
-
Start date:
08/12/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:

Description

Now all the benchmarks (Texas97, VCEGAR, Verilog2SMV/VIS) are added to Verilog Translator project and used there as tests.
In this project we should concentrate on tests for Retrascope.

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 #1

Updated by Sergey Smolov over 5 years ago

  • Subject changed from remove tests for Verilog Translator from project. to remove tests for Verilog Translator from project
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 #2

Updated by Mikhail Lebedev over 5 years ago

  • Status changed from New to Resolved
  • % Done changed from 0 to 100
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 #3

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Closed
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