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Bug #9215

ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found

Added by Sergey Smolov over 1 year ago. Updated over 1 year ago.

Status:
Rejected
Priority:
High
Target version:
Start date:
08/11/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

Module name: mem
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 47:19 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 50:19 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 147:5 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 148:12 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 171:5 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 179:5 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 required (...)+ loop did not match anything at input 'wire'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Starting the backend 'printer'...
module mem(.clkclk /* DECL: clk */, .TS_TS_ /* DECL: TS_ */, .TTTT /* DECL: TT */, .GBL_GBL_ /* DECL: GBL_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBB_DBB_ /* DECL: DBB_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, clk /* DECL: clk */, TS_ /* DECL: TS_ */, TT /* DECL: TT */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBB_ /* DECL: DBB_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, DBG1_ /* DECL: DBG1_ */);
  input clk;
  input TS_;
  input [00000000000000000000000000000000:00000000000000000000000000000100] TT;
  input GBL_;
  output AACK_;
  input ARTRY_;
  input DBB_;
  output TA_;
  output DRTRY_;
  input BG1_;
  input BG2_;
  input DBG1_;
  /* DECL: null */
  AddrStatus null
  (
  );
endmodule

Starting the backend 'design-elaborator'...
Expanding node 'MODULE(mem)'...
Bindings: {clk=clk, TS_=TS_, TT=TT, GBL_=GBL_, AACK_=AACK_, ARTRY_=ARTRY_, DBB_=DBB_, TA_=TA_, DRTRY_=DRTRY_, BG1_=BG1_, BG2_=BG2_, DBG1_=DBG1_}
Variables: {clk=DECLARATION(clk), TS_=DECLARATION(TS_), TT=DECLARATION(TT), GBL_=DECLARATION(GBL_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBB_=DECLARATION(DBB_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), DBG1_=DECLARATION(DBG1_)}
Module 'AddrStatus' cannot be found

To reproduce the bug, uncomment the runTest_PPC60X_bus_src_mem method in ru.ispras.verilog.parser.VerilogTexas97TestCase and run it.

History

#1

Updated by Alexander Kamkin over 1 year ago

  • Status changed from New to Rejected

Incorrect Verilog code.

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