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Bug #9214

ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found

Added by Sergey Smolov about 2 years ago. Updated about 2 years ago.

Status:
Rejected
Priority:
High
Target version:
Start date:
08/11/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

Module name: cpu
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 155:17 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 157:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 159:16 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 161:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 228:37 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 229:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 230:36 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 233:26 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 234:33 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 235:27 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 236:34 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 321:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 322:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 323:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 324:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 325:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 326:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 327:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 328:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 329:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 330:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 331:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 332:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 333:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 334:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 338:39 extraneous input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 339:28 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 341:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 342:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 346:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 347:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 348:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 349:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 350:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 351:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 352:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 353:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 354:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:40 mismatched input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:46 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 359:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 360:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 361:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 362:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 363:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 364:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 365:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 387:47 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 388:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 389:46 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 390:19 extraneous input ')' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 403:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 404:58 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 407:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 408:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 409:45 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 410:52 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 436:14 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 643:74 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 644:46 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 645:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 646:45 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 647:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 648:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 649:44 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 650:42 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 651:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 652:48 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 653:56 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 654:41 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 655:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 656:47 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 885:6 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 906:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 907:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 908:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:29 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:57 mismatched input ')' expecting COLON
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 939:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 941:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 943:16 mismatched input 'wire' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Starting the backend 'printer'...
module cpu(.clkclk /* DECL: clk */, .BR_BR_ /* DECL: BR_ */, .BG_BG_ /* DECL: BG_ */, .ABB_ABB_ /* DECL: ABB_ */, .ABB1_ABB1_ /* DECL: ABB1_ */, .TS_TS_ /* DECL: TS_ */, .TS1_TS1_ /* DECL: TS1_ */, .APAP /* DECL: AP */, .APE_APE_ /* DECL: APE_ */, .TTTT /* DECL: TT */, .TT1TT1 /* DECL: TT1 */, .TSIZTSIZ /* DECL: TSIZ */, .TBST_TBST_ /* DECL: TBST_ */, .TBST1_TBST1_ /* DECL: TBST1_ */, .TCTC /* DECL: TC */, .CI_CI_ /* DECL: CI_ */, .WT_WT_ /* DECL: WT_ */, .GBL_GBL_ /* DECL: GBL_ */, .GBL1_GBL1_ /* DECL: GBL1_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .ARTRY1_ARTRY1_ /* DECL: ARTRY1_ */, .SHD_SHD_ /* DECL: SHD_ */, .DBG_DBG_ /* DECL: DBG_ */, .DBB_DBB_ /* DECL: DBB_ */, .DBB1_DBB1_ /* DECL: DBB1_ */, .DPDP /* DECL: DP */, .DPE_DPE_ /* DECL: DPE_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, clk /* DECL: clk */, BR_ /* DECL: BR_ */, BG_ /* DECL: BG_ */, ABB_ /* DECL: ABB_ */, ABB1_ /* DECL: ABB1_ */, TS1_ /* DECL: TS1_ */, TS_ /* DECL: TS_ */, AP /* DECL: AP */, APE_ /* DECL: APE_ */, TT1 /* DECL: TT1 */, TT /* DECL: TT */, TSIZ /* DECL: TSIZ */, TBST1_ /* DECL: TBST1_ */, TBST_ /* DECL: TBST_ */, TC /* DECL: TC */, CI_ /* DECL: CI_ */, WT_ /* DECL: WT_ */, GBL1_ /* DECL: GBL1_ */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY1_ /* DECL: ARTRY1_ */, ARTRY_ /* DECL: ARTRY_ */, SHD_ /* DECL: SHD_ */, DBG_ /* DECL: DBG_ */, DBB_ /* DECL: DBB_ */, DBB1_ /* DECL: DBB1_ */, DP /* DECL: DP */, DPE_ /* DECL: DPE_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */);
  input clk;
  output BR_;
  input BG_;
  input ABB_;
  output ABB1_;
  output TS1_;
  input TS_;
  output [00000000000000000000000000000000:00000000000000000000000000000011] AP;
  output APE_;
  output [00000000000000000000000000000100:00000000000000000000000000000000] TT1;
  input [00000000000000000000000000000100:00000000000000000000000000000000] TT;
  output [00000000000000000000000000000010:00000000000000000000000000000000] TSIZ;
  output TBST1_;
  input TBST_;
  output [00000000000000000000000000000000:00000000000000000000000000000010] TC;
  output CI_;
  output WT_;
  output GBL1_;
  input GBL_;
  input AACK_;
  output ARTRY1_;
  input ARTRY_;
  output SHD_;
  input DBG_;
  input DBB_;
  output DBB1_;
  output [00000000000000000000000000000000:00000000000000000000000000000111] DP;
  output DPE_;
  input TA_;
  input DRTRY_;
  /* DECL: null */
  AddressTenure null
  (
  );
endmodule

Starting the backend 'design-elaborator'...
Expanding node 'MODULE(cpu)'...
Bindings: {clk=clk, BR_=BR_, BG_=BG_, ABB_=ABB_, ABB1_=ABB1_, TS_=TS_, TS1_=TS1_, AP=AP, APE_=APE_, TT=TT, TT1=TT1, TSIZ=TSIZ, TBST_=TBST_, TBST1_=TBST1_, TC=TC, CI_=CI_, WT_=WT_, GBL_=GBL_, GBL1_=GBL1_, AACK_=AACK_, ARTRY_=ARTRY_, ARTRY1_=ARTRY1_, SHD_=SHD_, DBG_=DBG_, DBB_=DBB_, DBB1_=DBB1_, DP=DP, DPE_=DPE_, TA_=TA_, DRTRY_=DRTRY_}
Variables: {clk=DECLARATION(clk), BR_=DECLARATION(BR_), BG_=DECLARATION(BG_), ABB_=DECLARATION(ABB_), ABB1_=DECLARATION(ABB1_), TS_=DECLARATION(TS_), TS1_=DECLARATION(TS1_), AP=DECLARATION(AP), APE_=DECLARATION(APE_), TT=DECLARATION(TT), TT1=DECLARATION(TT1), TSIZ=DECLARATION(TSIZ), TBST_=DECLARATION(TBST_), TBST1_=DECLARATION(TBST1_), TC=DECLARATION(TC), CI_=DECLARATION(CI_), WT_=DECLARATION(WT_), GBL_=DECLARATION(GBL_), GBL1_=DECLARATION(GBL1_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), ARTRY1_=DECLARATION(ARTRY1_), SHD_=DECLARATION(SHD_), DBG_=DECLARATION(DBG_), DBB_=DECLARATION(DBB_), DBB1_=DECLARATION(DBB1_), DP=DECLARATION(DP), DPE_=DECLARATION(DPE_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_)}
Module 'AddressTenure' cannot be found

To reproduce the bug, uncomment the runTest_PPC60X_bus_src_cpu method in ru.ispras.verilog.parser.VerilogTexas97TestCase and run it.

History

#1

Updated by Alexander Kamkin about 2 years ago

  • Status changed from New to Rejected

Incorrect Verilog code.

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