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Bug #9211

closed

java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193)

Added by Sergey Smolov over 6 years ago. Updated over 6 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
08/11/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
    at ru.ispras.verilog.parser.model.basis.VerilogPathItem.<init>(VerilogPathItem.java:41)
    at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:674)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:509)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:459)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:251)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:256)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:271)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:275)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:162)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:64)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:50)

To reproduce the bug, run any of the following test cases:
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Mux
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Add4
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Mux
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_ThreeBitReg
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_OneBitReg
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_DataMem
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_DataMem
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Clock
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_ZTest
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Clock
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_ZTest
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_SignExt
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_InstMem
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_SignExt
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Add4
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Register
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_RegFile
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_RegFile
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_OneBitReg
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_FiveBitReg
ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Register

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