Task #9198: Implicit declarations support - Verilog Translator - Open-Source Projects

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Task #9198

closed

Implicit declarations support

Added by Mikhail Lebedev over 5 years ago. Updated over 5 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Alexander Kamkin

Target version:

Start date:

08/09/2018

Due date:

% Done:

Estimated time:

Detected in build:

master

Published in build:

Description

Implement implicit declarations of nets and variables (chapter 4.5 of IEEE 1364-2005 Verilog standard).

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Updated by Mikhail Lebedev over 5 years ago

The following designs contain implicit declared variables:
vcegar-benchmarks/usb_phy/usb_phy_1.v : fs_ce vcegar-benchmarks/cache_coherence/three_processor_bin_2.v : is_snoop vcegar-benchmarks/cache_coherence/two_processor_bin_2.v : is_snoop texas97-benchmarks/DLX/SDLX/sdlx.v : IRRW texas97-benchmarks/p6bus/vl/p62_L_L_V01.v : CACHE_REQ

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