MicroTESK » MicroTESK for RISC-V

Test:

    TEST_CASE(6, a0, 0x54) do
      frcsr a0 # Originally frsr
    end

    TEST_CASE(7, a0, 0x14) do
      csrrci a0, fflags, 4
    end

Log:

test_6:
0x0000000080000158 frcsr a0
0x000000008000015c li t4, 0x54
0x0000000080000160 li gp, 0x6
Check: testreg(0x0000000000000054) == x29(0x0000000000000054)
0x0000000080000164 bne a0, t4, fail
test_7:
0x0000000080000168 csrrci a0, fflags, 0x4
fcsr = 54
csr = 14
imm = 4
~(zero_extend(XWORD, imm)) = fffffffffffffffb
0x000000008000016c li t4, 0x14
0x0000000080000170 li gp, 0x7
Check: testreg(0x0000000000000010) == x29(0x0000000000000014)
0x0000000080000174 bne a0, t4, fail
Jump to 0x000000008000042c
Error: Test failed (self check did not pass)!

Nml instruction action:

op csrrci(rd: X, csr: CSR_MODE, imm: card(5))
  syntax = format("csrrci %s, %s, 0x%x", rd.syntax, csr.syntax, imm)
  image  = format("%12s%5s111%5s1110011", csr.image, imm, rd.image)
  action = {
    if imm != 0 then
      csr = csr & ~zero_extend(XWORD, imm);
    endif;
    rd = zero_extend(XWORD, csr);
  }

ISA page 22:

The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-
extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer
register rs1 is treated as a bit mask that species bit positions to be cleared in the CSR. Any bit
that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is
writable. Other bits in the CSR are unaected.
The CSRRCI variants are similar to CSRRC

https://github.com/pervognsen/bitwise/blob/master/ion/riscv/riscv.ion :

 case CSRRCI:
        csr_val := read_csr(hart, csr);
        write_reg(hart, rd, csr_val);
        if (rs1) {
            write_csr(hart, csr, csr_val & ~imm);
        }