Bug #9165
Incorrect parameter value calculation at hierarchical Verilog description
Start date:
07/26/2018
Due date:
% Done:
0%
Estimated time:
Detected in build:
master
Platform:
Published in build:
Description
See the related Bug*Test5TestCase.java for more details. Look at "outreg" array element size - it should be 256 bit rather than 32.
Updated by
Updated by Alexander Kamkin over 2 years ago
- Status changed from New to Resolved
The path is defineparam is considered to be relative and to be deliberately absolutized.