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Bug #9165

Incorrect parameter value calculation at hierarchical Verilog description

Added by Sergey Smolov almost 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
High
Target version:
Start date:
07/26/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

See the related Bug*Test5TestCase.java for more details. Look at "outreg" array element size - it should be 256 bit rather than 32.

History

#1

Updated by Sergey Smolov almost 2 years ago

The related testcase is Bug9165Test1TestCase.java

#2

Updated by Alexander Kamkin almost 2 years ago

  • Status changed from New to Resolved

The path is defineparam is considered to be relative and to be deliberately absolutized.

#3

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Resolved to Verified
#4

Updated by Sergey Smolov almost 2 years ago

  • Status changed from Verified to Closed

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