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Bug #9160

closed

ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
07/25/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

Run the specified jUnit testcase and see the log ending:

Starting the backend 'design-elaborator'...
Module 'mips_16_core_top' cannot be found
Design variables: []
Elaborated variables: {}
Starting the backend 'printer'...

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 #1

Updated by Sergey Smolov over 5 years ago

  • Priority changed from Normal to High
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 #2

Updated by Alexander Kamkin over 5 years ago

  • Status changed from New to Resolved

There was a bug in handling multilevel includes.

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 #3

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Verified
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 #4

Updated by Sergey Smolov over 5 years ago

  • Status changed from Verified to Closed
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