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Bug #9160

ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found

Added by Sergey Smolov about 2 years ago. Updated about 2 years ago.

Status:
Closed
Priority:
High
Target version:
Start date:
07/25/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

Run the specified jUnit testcase and see the log ending:

Starting the backend 'design-elaborator'...
Module 'mips_16_core_top' cannot be found
Design variables: []
Elaborated variables: {}
Starting the backend 'printer'...

History

#1

Updated by Sergey Smolov about 2 years ago

  • Priority changed from Normal to High
#2

Updated by Alexander Kamkin about 2 years ago

  • Status changed from New to Resolved

There was a bug in handling multilevel includes.

#3

Updated by Sergey Smolov about 2 years ago

  • Status changed from Resolved to Verified
#4

Updated by Sergey Smolov about 2 years ago

  • Status changed from Verified to Closed

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