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Bug #9142

closed

Case expression type mismatch in opencores/mips16/instruction_mem.v

Added by Mikhail Lebedev almost 6 years ago. Updated almost 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine
Target version:
-
Start date:
07/19/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
1.1.1-beta-190722

Description

The model checker fails to process the generated smv model with the following error:

TYPE ERROR file instruction_mem.smv: line 317 : illegal operand types of "=" : unsigned word[8] and unsigned word[4]

It is caused by:

rom_addr : word[8]
...
rom_addr = 0d4_12

In Verilog source:

wire [7 : 0] rom_addr;
...
case (rom_addr)
4'b0000: ...
...

Case value size doesn't match the variable size. This value is transferred to the smv model without any transformation.

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