Bug #9142: Case expression type mismatch in opencores/mips16/instruction_mem.v - Retrascope - Open-Source Projects

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Bug #9142

closed

Case expression type mismatch in opencores/mips16/instruction_mem.v

Added by Mikhail Lebedev almost 6 years ago. Updated over 4 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Sergey Smolov

Category:

Engine

Target version:

Start date:

07/19/2018

Due date:

% Done:

100%

Estimated time:

Detected in build:

master

Platform:

Published in build:

1.1.1-beta-190722

Description

The model checker fails to process the generated smv model with the following error:
TYPE ERROR file instruction_mem.smv: line 317 : illegal operand types of "=" : unsigned word[8] and unsigned word[4]
It is caused by:
rom_addr : word[8] ... rom_addr = 0d4_12
In Verilog source:
wire [7 : 0] rom_addr; ... case (rom_addr) 4'b0000: ... ...
Case value size doesn't match the variable size. This value is transferred to the smv model without any transformation.

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Updated by Sergey Smolov over 5 years ago

Status changed from New to Open

The problem comes from the source Verilog code:

`define    INSTR_MEM_ADDR_WIDTH    8
...
wire [`INSTR_MEM_ADDR_WIDTH-1 : 0] rom_addr = pc[`INSTR_MEM_ADDR_WIDTH-1 : 0];
...
always @(*)
    case (rom_addr)
        4'b0000: instruction = 16'b1001001000001000;
        4'b0001: instruction = 16'b1001010001001000;
        4'b0010: instruction = 16'b1001011010001000;
        4'b0011: instruction = 16'b0001100010011000;
        4'b0100: instruction = 16'b1011100001000010;
        4'b0101: instruction = 16'b1010101001000010;
        4'b0110: instruction = 16'b0010110100101000;
        4'b0111: instruction = 16'b1100000110111000;
        4'b1000: instruction = 16'b1001111111000001;
        4'b1001: instruction = 16'b0000000000000000;
        4'b1010: instruction = 16'b0000000000000000;
        4'b1011: instruction = 16'b0000000000000000;
        4'b1100: instruction = 16'b0000000000000000;
        4'b1101: instruction = 16'b0000000000000000;
        4'b1110: instruction = 16'b0000000000000000;
        4'b1111: instruction = 16'b0000000000000000;
        default: instruction = 16'b0000000000000000;
    endcase

Probably, it should be transformed at some stage.

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