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Bug #9010
closedTexas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException
Start date:
06/27/2018
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Platform:
Published in build:
Description
java.lang.IllegalArgumentException at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53) at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38) at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95) at ru.ispras.verilog.parser.processor.VerilogExprTransformer$2.apply(VerilogExprTransformer.java:169) at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166) at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226) at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173) at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123) at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93) at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54) at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230) at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62) at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:159) at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onIfStatementBegin(VerilogTransformer.java:96) at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$20.onBegin(VerilogNodeVisitor.java:469) at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700) at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100) at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85) at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53) at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44) at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88) at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185) at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173) at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36) at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56) at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169) at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45) at ru.ispras.verilog.parser.sample.VerilogPrinterTest.runTest(VerilogPrinterTest.java:49)
Updated by Sergey Smolov almost 6 years ago
It seems that "is_snoop" variable has UNKNOWN data type here.
Updated by Sergey Smolov almost 6 years ago
- Status changed from New to Open
- Assignee set to Sergey Smolov
Updated by Sergey Smolov over 5 years ago
- Status changed from Open to Resolved
- % Done changed from 0 to 100
The UNKNOWN datatype was fixed in Verilog Translator.
Updated by Sergey Smolov over 5 years ago
- Status changed from Resolved to Closed
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