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Bug #8990

vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions

Added by Sergey Smolov over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
High
Target version:
Start date:
06/22/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The following Verilog code fragment:

`MST_ADDR_DATA:
       begin
          if (read_tmp == 1)
         mst_data_tmp = DIN;
          //else
        // mst_data_tmp = mst_datain;
          if ((ACK == `ERR)||(TOUT == 1)) 
         begin
            state = `MST_IDLE;
            st_mst_abort_tmp = 1;
            lock_tmp = 0;
            req_tmp = 0;
            addr_tmp = {30{1'b0}};
            opc_tmp = 4'b0000;
            read_tmp = 0;
         end
          else if (ACK == `RTR) 
         state = `MST_RTRCT;
           else if (((ACK==`RDM)||(ACK==`RDY))&& (lock_tmp == 1))
              begin
             req_tmp = 0;
             addr_tmp = mst_addr;
             opc_tmp = (mst_size==1)? 4'b0001:4'b0000;
             read_tmp = (mst_rd == 1)? 1 : 0;
             lock_tmp = mst_lock;
             state = `MST_ADDR_DATA;
              end
            else if (ACK==`WAT)
               begin
                  state = `MST_ADDR_DATA;
               end
                 else
                begin
                   req_tmp = 0;
                   addr_tmp = {30{1'b0}};
                   opc_tmp = 4'b0000;
                   read_tmp = 0;
                   lock_tmp = 0;
                   state = `MST_DATA;
                end
       end

is incorrectly translated by VeriTrans into the following:

100:
        begin
          if(((acknowledge == 1) || (timeout == 1)))
            begin
               state2 = 000;
               M_cnt_1.st_mst_abort_tmp = 1;
               M_cnt_1.lock_tmp = 0;
               M_cnt_1.req_tmp = 0;
               M_cnt_1.addr_tmp = 000000000000000000000000000000;
               M_cnt_1.opc_tmp = 0000;
               M_cnt_1.read_tmp = 0;
            end
          else
            if((acknowledge == 1))
               state2 = 101;
            else
              if((acknowledge == 1))
                begin
                  if((M_cnt_1.read_tmp == 1))
                     mst_data_tmp2 = data_slave2master;
                  else
                    begin
                    end
                  end
                   M_cnt_1.req_tmp = 0;
                   state2 = 100;
                   M_cnt_1.addr_tmp = 000000000000000000000000000000;
                   M_cnt_1.opc_tmp = 0000;
                   M_cnt_1.read_tmp = 0;
                   M_cnt_1.lock_tmp = 0;
                end
              else
                if(((M_cnt_1.mst_rd == 1) || (M_cnt_1.mst_wr == 1)))
                  begin
                     M_cnt_1.req_tmp = 1;
                     state2 = 001;
                  end
                else
                  begin
                     M_cnt_1.req_tmp = 0;
                     M_cnt_1.st_mst_abort_tmp = 0;
                     M_cnt_1.lock_tmp = 0;
                     M_cnt_1.addr_tmp = 000000000000000000000000000000;
                     M_cnt_1.opc_tmp = 0000;
                     M_cnt_1.read_tmp = 0;
                     state2 = 000;
                  end
                end
              end
            end
          end
        end

The erroneous point is at two nested "acknowledge == 1" switch statements which are not appear in the original module. The module code is attached; also it can be found in the Retrascope MC Benchmark project test suite.


Files

main_1.v (23.6 KB) main_1.v Sergey Smolov, 06/22/2018 06:37 PM

Related issues

Related to Retrascope - Bug #8972: Case value RetrascopeException in VcegarPiBusCfgGraphMlTestCaseClosed06/19/2018

Actions

History

#1

Updated by Sergey Smolov over 1 year ago

  • Related to Bug #8972: Case value RetrascopeException in VcegarPiBusCfgGraphMlTestCase added
#2

Updated by Sergey Smolov over 1 year ago

  • Priority changed from High to Normal
#3

Updated by Sergey Smolov over 1 year ago

  • Priority changed from Normal to High
#4

Updated by Alexander Kamkin over 1 year ago

  • Status changed from New to Resolved
#5

Updated by Sergey Smolov over 1 year ago

  • Status changed from Resolved to Verified
#6

Updated by Sergey Smolov over 1 year ago

  • Status changed from Verified to Closed

Verilog Translator produces the described AST because of non equal datatypes of 'acknowledge' signal (1-bit vector) and related constants (3-bit vector).

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