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Bug #8974

IllegalArgumentException in VcegarSdlxCfgGraphMlTestCase

Added by Mikhail Lebedev 11 months ago. Updated 4 months ago.

Status:
Verified
Priority:
Normal
Assignee:
Category:
Engine (Parser)
Target version:
Start date:
06/19/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

This error appears in VcegarSdlxCfgGraphMlTestCase of the Retrascope-MC-Benchmark project.
Log:

java.lang.IllegalArgumentException: Null value for target: NextState


at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.retrascope.model.basis.Assignment.<init>(Assignment.java:67)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.createAssignment(VerilogCfgProcessBuilder.java:297)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.parseAssignment(VerilogCfgProcessBuilder.java:343)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.onAssignStatementBegin(VerilogCfgProcessBuilder.java:488)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.start(VerilogCfgBuilder.java:82)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
at ru.ispras.retrascope.parser.verilog.VerilogParser.parse(VerilogParser.java:103)
at ru.ispras.retrascope.parser.basis.HdlParser.start(HdlParser.java:112)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:111)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.Retrascope$ToolRun.start(Retrascope.java:215)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:456)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:373)

Corresponding Verilog:

src/main/verilog/vcegar-benchmarks/sdlx/control1.v

History

#1

Updated by Sergey Smolov 11 months ago

  • % Done changed from 0 to 100
  • Status changed from New to Resolved

Fixed in 25b0ea64

#2

Updated by Mikhail Lebedev 11 months ago

  • Status changed from Resolved to Verified
#3

Updated by Sergey Smolov 9 months ago

  • Target version set to 1.0
#4

Updated by Sergey Smolov 4 months ago

  • Category set to Engine (Parser)

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