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Bug #8912

file ram.smv: line 332: variable is assigned more than once: m_ram.mem0

Added by Sergey Smolov 12 months ago. Updated 4 months ago.

Status:
Resolved
Priority:
Normal
Assignee:
Category:
Engine (Transformer)
Target version:
Start date:
06/01/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The nuXmv model checker fails to elaborate designs that assign same variable in different processes.
See ram.v & fifo.v Verilog modules.


Related issues

Related to Retrascope - Feature #9039: Support for designs that assign to variable more than onceResolved06/29/2018

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History

#1

Updated by Sergey Smolov 11 months ago

  • Assignee set to Sergey Smolov
#2

Updated by Sergey Smolov 11 months ago

  • Related to Feature #9039: Support for designs that assign to variable more than once added
#3

Updated by Sergey Smolov 11 months ago

  • Assignee changed from Sergey Smolov to Mikhail Lebedev
#4

Updated by Sergey Smolov 10 months ago

  • % Done changed from 0 to 100
  • Assignee changed from Mikhail Lebedev to Sergey Smolov
  • Status changed from New to Resolved

Fixed in 7cf2a84e

#5

Updated by Sergey Smolov 4 months ago

  • Category set to Engine (Transformer)

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