Bug #8912
file ram.smv: line 332: variable is assigned more than once: m_ram.mem0
Start date:
06/01/2018
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Platform:
Published in build:
1.1.1-beta-190722
Description
The nuXmv model checker fails to elaborate designs that assign same variable in different processes.
See ram.v & fifo.v Verilog modules.
Related issues
History
Updated by Sergey Smolov over 2 years ago
- Related to Feature #9039: Support for designs that assign to variable more than once added
Updated by Sergey Smolov over 2 years ago
- % Done changed from 0 to 100
- Assignee changed from Mikhail Lebedev to Sergey Smolov
- Status changed from New to Resolved
Fixed in 7cf2a84e
Updated by Sergey Smolov over 1 year ago
- Published in build set to 1.1.1-beta-190722
- Status changed from Resolved to Closed