Verilog Translator

The stack trace:

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:266)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:181)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_08_02_1(VerilogIeeeTestCase.java:1119)

// IEEE Std 1364-2005
//   12. Hierarchical structures
//     12.8 Elaboration
//       12.8.2 Early resolution of hierarchical names
//         In order to comply with this algorithm, hierarchical names in some defparam statements
//         will need to be resolved prior to the full elaboration of the hierarchy. It is possible
//         that when elaboration is complete, rules for name resolution would dictate that a
//         hierarchical name in a defparam statement would have resolved differently had early
//         resolution not been required. This could result in a situation where an identical
//         hierarchical name in some other statement in the same scope would resolve differently
//         from the one in the defparam statement. Below is an example of a design
//         that has this problem.

module m;
  m1 n();
endmodule

module m1;
  parameter p = 2;

  defparam m.n.p = 1;

  initial $display (m.n.p);

  generate
    if (p == 1) begin : m
      m2 n();
    end
  endgenerate

endmodule

module m2;
  parameter p = 3;
endmodule