Verilog Translator

The stack trace:

java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i)
    at ru.ispras.fortress.expression.NodeOperation.getParams(NodeOperation.java:260)
    at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:196)
    at ru.ispras.fortress.expression.Node.isType(Node.java:177)
    at ru.ispras.fortress.expression.ExprUtils.isType(ExprUtils.java:84)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:214)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:159)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:170)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:189)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:79)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
    at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
    at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
    at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
    at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_01_2(VerilogIeeeTestCase.java:1054)

The target Verilog module:

// IEEE Std 1364-2005
//   12. Hierarchical structures
//     12.4 Generate constructs
//       12.4.1 Loop generate constructs
//         A parameterized gray-code–to–binary-code converter module using a loop to generate
//         continuous assignments.

module gray2bin1 (bin, gray);
  parameter SIZE = 8;
  // this module is parameterizable
  output [SIZE-1:0] bin;
  input [SIZE-1:0] gray;
  genvar i;
  generate
    for (i=0; i<SIZE; i=i+1) begin :bit
      assign bin[i] = ^gray[SIZE-1:i];
      // i refers to the implicitly defined localparam whose
      // value in each instance of the generate block is
      // the value of the genvar when it was elaborated.
    end
  endgenerate
endmodule